Effective medium semiconductor cavities for rf applications

ABSTRACT

An electronic package apparatus is formed from a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.

The present application relates generally toradio frequency (RF) devices, and more specifically to the integration of RF devices into semiconductor substrates.

Wireless communications use an antenna to transmit and receive electromagnetic (EM) signals. The antenna is typically driven by an integrated circuit (IC) or other discrete device. This IC or driver chip may be configured within a package on a printed circuit (PC) board, for example, along with other circuitry. The EM signal from the driver chip reaches the antenna via internal wiring or other metallization.

There is an increasing demand for compact radio communications systems having integrated transmitter, receiver, transceiver and antenna systems, which enable high data transmission rates, high volume, low power consumption, low weight, and low cost. As operating frequencies increase, the manufacture and assembly of such systems becomes increasingly difficult due to the requirements of high-precision machining and accurate alignment.

Radio frequency devices, including devices operating at 10 GHz and greater, are beneficially integrated directly onto a semiconductor substrate such as a silicon substrate. However, in view of the relatively large dielectric constant of silicon (k˜11.9), locating an antenna for such devices proximate to such a high dielectric constant material can adversely affect performance Improved performance can be achieved by locating antennae proximate to an air gap (or cavity).

A cavity requires opposing top and bottom surfaces to enclose a space, and in most device architectures these surfaces need to be mechanically supported. In conventional structures, a cavity is initially formed in one substrate and then a second (top) substrate is attached to the first substrate to enclose the cavity. It is difficult and costly, however, to ensure proper alignment of the second substrate.

Thus, it would be advantageous to provide a method and structure for providing cavities in a semiconductor substrate that are configured to house RF elements such as driver chips and antennae and that obviate the need for aligning and securing a second substrate to enclose the cavity.

SUMMARY

In accordance with embodiments of the present application, an electronic package apparatus includes a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.

A method of making an electronic package apparatus includes etching trenches in a front surface of a semiconductor substrate, where the trenches have a lateral dimension of less than 0.1 cm, and at least partially filling the trenches with a first dielectric material. The method further involves depositing a layer of a second dielectric material over the front surface of the substrate, and etching a back surface of the semiconductor substrate to expose the first dielectric material. A layer of a third dielectric material is deposited over the back surface of the substrate, and a cavity having a top surface, a bottom surface, and a sidewall surface is etched in the semiconductor substrate such that the first dielectric material forms at least one spacer extending between the bottom surface to the top surface.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The following detailed description of specific embodiments of the present application can be best understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals and in which:

FIG. 1A is a top-down plan view showing a trench architecture for the formation of a chip cavity, a stripline cavity, and an antenna cavity within a semiconductor substrate;

FIG. 1B is a cross-sectional view of FIG. 1A showing the formation of trenches in the semiconductor substrate and the subsequent deposition of a dielectric material and a semiconductor material within the trenches;

FIG. 2A shows the formation of metal layers within a through substrate via (TSV) and a trench located peripheral to the antenna cavity of FIG. 1A;

FIG. 2B shows the reopening of select vias and trenches and the conformal deposition of metal layers therein;

FIG. 3A depicts the formation of conductive vias and a conductive stripline extending between the chip cavity and the antenna cavity;

FIG. 3B shows formation of the conductive stripline within a dielectric layer formed over a front surface of the semiconductor substrate;

FIG. 4A is a plan view showing the intermediate architecture of FIG. 3A;

FIG. 4B depicts the lamination of a transparent layer to the dielectric layer of FIG. 3B, and thinning of the back surface of the semiconductor substrate to expose the filled vias and trenches;

FIG. 5A shows deposition of a back metal layer and the formation of an optional etch port;

FIG. 5B shows the formation of plural wiring layers including a back metal layer embedded within a dielectric layer formed over the back surface of the semiconductor substrate;

FIG. 6A shows the selective etching of plural cavities within the semiconductor substrate; and

FIG. 6B shows a chip cavity, stripline cavity, and antenna cavity formed within the semiconductor substrate and supported by oxide pillars.

DETAILED DESCRIPTION

Reference will now be made in greater detail to various embodiments of the subject matter of the present application, some embodiments of which are illustrated in the accompanying drawings. The same reference numerals will be used throughout the drawings to refer to the same or similar parts.

Embodiments relate to apparatus and methods for packaging integrated circuit chips with integrated antennae to form high-performance radio/wireless communication systems for millimeter wave applications, e.g., for voice and data communications. Antennae such as planar antennae are incorporated into a semiconductor substrate proximate to a cavity structure and connected to an on-board IC chip.

Various chip types may be packaged with one or more antenna. Example IC chips include integrated transmitter circuits, integrated receiver circuits, integrated transceiver circuits, and/or other support circuitry, which can be incorporated into various types of devices for wireless communication applications.

A cavity structure for an RF device is formed in a semiconductor substrate such as a silicon substrate where opposing top and bottom surfaces of one or more cavities formed in the substrate are supported by a network of pillars or ridges that span the cavity between the opposing surfaces. In embodiments, the length and/or width of the pillars or ridges is less than 0.1□, where □ is the operational wavelength of the device. For instance, an extremely high frequency device may operate at a frequency of 30 to 300 GHz (1 cm to 1 mm), and the length and/or width of the pillars or ridges in such devices may be less than 0.1 cm and less than 0.1 mm, respectively.

As used herein, a pillar is a columnar structure having a (vertical) height that is greater than both its length and its width. A ridge is a narrow, raised structure having a (vertical) height that is greater than at least one of its length and its width. Pillars and ridges may be collectively referred to as spacers. According to various embodiments, at least one of the length dimension or the width dimension of an example spacer may be 2, 5, 10, 20, 50, 100 or 200 microns, including ranges between any of the foregoing values.

By providing a network of spacers having one or both cross-sectional dimensions substantially less than an operational wavelength of the device, the effective dielectric constant of a cavity may be represented as a volume average of the dielectric constant of the gas (or vacuum) that fills the cavity and the material(s) used to form the spacers.

In embodiments the top and bottom surfaces of the cavity derive from a single semiconductor substrate, such as a silicon wafer, and are supported (spanned) by a network of thin silicon oxide pillars or ridges. For instance, the top and bottom surfaces of the cavity may comprise silicon wafer-process compatible layers, including one or more deposited layers such as dielectric layers, or incumbent substrate material such as silicon (Si). A cavity height may range from 50 to 750 microns. The cavity height of different cavities (e.g., chip cavity and antenna cavity) may be the same or different. Expressed as a percentage of the total thickness of the semiconductor substrate, a cavity height may be 5, 10, 20, 50, 75, 90, 95 or 100% of the substrate thickness, including ranges between any of the foregoing values.

The spacers may be aligned perpendicular to the direction of the electric field that passes through the cavity during use of the device such that the effective dielectric constant of the cavity is near that of free space. A cavity may be closed or substantially closed.

Schematic views illustrating an example method of forming cavity structures in a semiconductor substrate are shown in FIGS. 1-6, where FIGS. 1A-6A are top-down plan views and FIGS. 1B-6B are corresponding cross-sectional views.

Shown in FIG. 1A is a semiconductor substrate 100 such as a silicon substrate having formed therein plural trenches 200 that define, in the illustrated embodiment, a chip cavity area 10, a stripline cavity area 20, an antenna cavity area 30, and a through substrate via (TSV) 40. Trenches 200 also define the location of a plurality of spacers, e.g., within antenna cavity area 30. The illustrated embodiment includes multiple ring-shaped trenches within the antenna cavity area 30.

Substrate 100 may be a semiconductor material such as silicon or a silicon-containing material, including a bulk substrate. Silicon-containing materials include, but are not limited to, single crystal Si, polycrystalline Si, single crystal silicon germanium (SiGe), polycrystalline silicon germanium, silicon doped with carbon (Si:C), amorphous Si, as well as combinations and multi-layers thereof. As used herein, the term “single crystal” denotes a crystalline solid in which the crystal lattice of the entire sample is substantially continuous and substantially unbroken to the edges of the sample with substantially no grain boundaries.

In embodiments, substrate 100 may be a semiconductor-on-insulator (SOI) substrate. Further, substrate 100 is not limited to silicon-containing materials, as the substrate 100 may comprise other semiconductor materials, including Ge and compound semiconductors such as GaAs, InAs, and other like semiconductors.

Referring to FIG. 1B, trenches 200 are formed in substrate 100 using conventional photolithography and etching methods. Photolithography includes forming a layer of photoresist material (not shown) atop a material or material stack to be patterned. The photoresist material may include a positive-tone photoresist composition, a negative-tone photoresist composition, or a hybrid-tone photoresist composition. A layer of photoresist material may be formed by a deposition process such as, for example, spin-on coating.

The deposited photoresist is then subjected to a pattern of irradiation, and the exposed photoresist material is developed utilizing a conventional resist developer. In the instant embodiment, this provides a patterned layer of photoresist atop a portion of the substrate 100. The pattern provided by the patterned photoresist material is thereafter transferred into the underlying material layer or material layers utilizing at least one pattern transfer etching process.

The pattern transfer etching process may be an isotropic etch or an anisotropic etch. In embodiments, a dry etching process such as, for example, reactive ion etching can be used. In other embodiments, a wet chemical etchant can be used. In still further embodiments, a combination of dry etching and wet etching can be used. For example, trenches 200 may be formed using a deep reactive-ion etching (DRIE) process and, when initially formed, extend only part way through the substrate.

Still with reference to FIG. 1B, a dielectric layer 210 such as a layer of thermal oxide is formed over exposed sidewalls of the trenches 200. The trenches are then capped with a wet etch stop material 220 such as polysilicon, silicon nitride, SiCN or SiCOH. A thermal oxide layer may be formed on exposed surfaces of the trenches 200 by oxidizing the silicon substrate at 1000-1200° C. in an oxidizing environment. The thickness of dielectric layer 210 may range from 5 microns up to 50% of the width of a trench 200.

FIG. 1B shows an intermediate architecture after deposition and planarization of the dielectric layer 210 and etch stop material 220. “Planarization” is a material removal process that employs at least mechanical forces, such as frictional media, to produce a substantially two-dimensional surface. A planarization process may include chemical mechanical polishing (CMP) or grinding. Chemical mechanical polishing (CMP) is a material removal process that uses both chemical reactions and mechanical forces to remove material and planarize a surface.

As shown in FIGS. 2A and 2B, if through vias or metal cavity walls are desired, one or more trenches 200 may be re-opened and plated or otherwise at least partially filled with a one or more conductive materials such as copper or tungsten. Reopening of the trenches may be performed using dry etching process, e.g., reactive ion etching, a wet chemical etch, or a combination of dry etching and wet etching. A barrier layer, e.g., tantalum/tantalum nitride or titanium/titanium nitride may be initially deposited within re-opened trenches 200, followed by deposition of a metal layer by chemical vapor deposition optionally followed by electroplating. The thickness of metallization 240 may range from 0.05 microns up to 50% of the width of a trench 200. Then, a further CMP step may be used to planarize a top surface of the substrate 100, having formed therein trenches comprising a dielectric layer 210 and trenches comprising one or more layers of metallization 240. During a CMP step, etch stop material 220 may be used as a stopping layer. Following CMP, deposited metal remaining outside the trenches can be removed using reactive ion etching or RIE or wet etching.

After planarization, as depicted in FIGS. 3A and 3B, a dielectric layer 310 may be formed over a top surface of the substrate 100 covering (at least partially) filled trenches 200. Contact vias 320, strip metallization 330, or other wiring may be formed within or on dielectric layer 310. For example, using a dry and/or wet etch, dielectric layer 310 may be locally recessed to create openings into which, as shown in FIG. 3B, a conductive material is deposited, planarized, recessed and patterned to form embedded metal structures. A plan view of the architecture of FIG. 3B is depicted in FIG. 3A, which shows the strip metallization 330 extending from the chip cavity area 10 to the antenna cavity area 30. Illustrated contact vias 320 are formed in chip cavity area 10.

Dielectric layer 310 may comprise a dielectric material such as a low-k dielectric material. Exemplary dielectric materials include silicon oxide, silicon nitride, and silicon oxynitride. Exemplary low-k dielectric materials include, but are not limited to, amorphous carbon, fluorine-doped oxides, carbon-doped oxides, SiCOH or SiBCN. Commercially-available low-k dielectric products and materials include Dow Corning's SiLK™ and porous SiLK™, Applied Materials' Black Diamond™, Texas Instrument's Coral™ and TSMC's Black Diamond™ and Coral™. As used herein, a low-k dielectric material has a dielectric constant less than that of silicon oxide.

The dielectric layer 310 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD) or spin-coating. In embodiments, the dielectric material may be self-planarizing, or the top surface of the dielectric layer 310 can be planarized by chemical mechanical polishing (CMP). The thickness of the dielectric layer 310 layer may range from 0.05 to 3 microns.

Contact vias 320 and strip metallization 330 may include a conductive material such as polysilicon, silicon-germanium, a conductive metal such as Al, W, Cu, Ti, Ta, W, Pt, Ag, Au, Ru, Ir, Rh and Re, alloys of conductive metals, e.g., Al—Cu, silicides of a conductive metal, e.g., W silicide, and Pt silicide, or other conductive metal compounds such as TiN, TiC, TiSiN, TiTaN, TaN, TaAlN, TaSiN, TaRuN, WSiN, NiSi, CoSi, as well as combinations thereof.

Metal layers including contact vias 320, strip metallization 330, and dipole antenna 332 may be formed utilizing a conventional deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering and plating. A tungsten metal layer, for instance, may be deposited by chemical vapor deposition using tungsten hexafluoride as a gaseous reactant.

Then, as shown in FIGS. 4A and 4B, a transparent layer 420 is bonded to the top surface of the dielectric layer 310. The transparent layer 420 may be thermally bonded using a binding layer 410, such as a polyimide layer, which is deposited on the top surface of the dielectric layer 310. For instance, binding layer 410 may be applied to the dielectric layer surface using a spin-coating technique. In embodiments, transparent layer 420 is permanently bonded. In alternate embodiments, transparent layer 420 is temporarily bonded. Removal processes may use solvents, laser ablation, or heat to soften the binding layer 410. As will be appreciated by those skilled in the art, the composition and thickness of the transparent layer 420 may be selected to provide desired antenna properties, including transmittance of electromagnetic radiation there through. Transparent layer 420 may comprise a light weight, low RF-loss, RF transparent glass or a ceramic. Advantageously, the transparent layer need not be aligned with a high degree of precision.

In a step that may precede or follow lamination of the transparent layer, the substrate is backside etched or otherwise thinned to expose dielectric 210 and metallization 240. In embodiments, a dry etching process such as reactive ion etching can be used. For example, plasma etching of silicon may be performed using a fluorine-containing (e.g., CF₄) plasma. In other embodiments, a wet chemical etchant can be used. In still further embodiments, a combination of dry etching and wet etching can be used. In still further embodiments, a combination of mechanical grinding followed by reaction ion etching can be used.

After completion of the backside etch, as illustrated in FIGS. 5A and 5B, a dielectric layer is formed over the bottom surface of the substrate. In some embodiments, the foregoing plasma processing continues to form dielectric layer 510. By way of example, when the substrate etch is complete, the fluorine-containing gas (e.g., CF₄) is turned off and oxygen (or water vapor), or nitrogen, or mixtures thereof, are supplied with the plasma to form dielectric layer 510. The oxygen and/or nitrogen react with silicon to form silicon oxide, silicon nitride, and/or silicon oxynitride. Dielectric layer 510 provides mechanical support to the substrate and electrical isolation for one or more backside conductive layers. The thickness of the dielectric layer 510 layer may range from 0.05 to 1 microns. As is known to those skilled in the art, one or more conductive layers may be deposited to form contact pads 520 and reflector or patch antenna 530 on the backside of the substrate.

A selective etch such as a wet etch or a plasma-based or xenon difluoride etch is then used to remove silicon from between the spacers forming cavities 610, 620, 630, as shown in FIGS. 6A and 6B. The selective etch does not remove dielectric layers 210, 310, 510 or metallization 240, 520, 530. In the illustrated embodiment, chip cavity 610 is open at a backside of the structure, while stripline cavity 620 and antenna cavity 630 are substantially closed cavities.

Removal of silicon (or other semiconductor materials) from within a substantially closed cavity such within stripline cavity area 20 and antenna cavity area 30 may be performed by way of an etch port 312 through which a suitable etching chemistry can be introduced and etch products exhausted. In various embodiments, one or more etch ports 312 may be located on one or both of the front side and the backside of the substrate 100. In embodiments, after etching of the semiconductor material, the etch port(s) 312 can be closed such as by localized deposition of a dielectric to form a closed cavity.

Various wet etch chemistries may be used to etch silicon, for example. Single crystal and polycrystalline silicon may be etched using a mixture of hydrofluoric acid (HF) and nitric acid (HNO₃). These etchants generally provide isotropic etching. Without wishing to be bound by theory, the etching is initiated by HNO₃, which forms an oxide layer on the silicon, while the HF then dissolves the oxide. Water may be used as a diluent, and acetic acid may be used as a buffering agent.

In lieu of a wet etch chemistry, gaseous etchants such as xenon difluoride (XeF₂) may be used to etch silicon. With a gas-based etchant, the etch ports can be small (e.g., less than 0.1 microns in diameter), which allows the etch ports to be easily closed, for example, in vacuum using CVD silicon oxide.

Chip cavity 610, stripline cavity 620, and antenna cavity 630 can be square, rectangular, circular or oval, and may have a real dimensions ranging from 10 microns to 10 mm A chip cavity 610 may have a length and width of 1 mm and 1.5 mm, for example. An antenna cavity 620 may have a length and a width each equal to 2 mm.

Selective etching of the silicon (or other like semiconductor material) reveals spacers 700 comprising dielectric 210 and structures 710 comprising metallization 240 that extend from a top surface to a bottom surface of respective cavities. In embodiments, top and/or bottom cavity surfaces may comprise un-etched portions of the semiconductor substrate, dielectric 310, dielectric 510, metallization 520 and/or metallization 530. In embodiments, spacers 700 define sidewalls of the cavity. In embodiments, spacers 700 are set away from the sidewalls.

As illustrated in FIG. 6A, plural spacers 700 may be arranged parallel to each other. A distance between adjacent spacers may range from 10 microns to 500 microns, e.g., 10, 20, 50, 100, 200 or 500 microns, including ranges between any of the foregoing values.

In embodiments, RF chips (not shown) are bonded into the chip cavities and optionally embedded in underfill. A solder ball may be placed over each backside contact pad 520. The substrate may then be diced into individual die. Different die may contain different components.

Millimeter wave RF antennas and resonators may be integrated into silicon processing by introducing cavities into a silicon substrate. The cavities compensate for the relatively high dielectric constant of silicon and enable effective antenna coupling to free space, and are advantageously formed without using a second (cavity-closing) substrate, thus obviating alignment challenges that are incumbent to such a second substrate approach.

As used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a “cavity” includes examples having two or more such “cavities” unless the context clearly indicates otherwise.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that any particular order be inferred. Any recited single or multiple feature or aspect in any one claim can be combined or permuted with any other recited feature or aspect in any other claim or claims.

It will be understood that when an element such as a layer, region or substrate is referred to as being formed on, deposited on, or disposed “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, no intervening elements are present.

While various features, elements or steps of particular embodiments may be disclosed using the transitional phrase “comprising,” it is to be understood that alternative embodiments, including those that may be described using the transitional phrases “consisting” or “consisting essentially of,” are implied. Thus, for example, implied alternative embodiments to a pillar that comprises silicon oxide include embodiments where a pillar consists essentially of silicon oxide and embodiments where a pillar consists of silicon oxide.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and their equivalents. 

1.-10. (canceled)
 11. A method of making an electronic package apparatus, comprising: etching trenches in a front surface of a semiconductor substrate, the trenches having at least one lateral dimension less than 0.1 cm; at least partially filling the trenches with a first dielectric material; depositing a layer of a second dielectric material over the front surface of the substrate; etching a back surface of the semiconductor substrate to expose vertical sidewalls of the first dielectric material, wherein said etching forms a cavity in the semiconductor substrate, the cavity having an open portion bound by a bottom surface, and the exposed vertical sidewalls of the first dielectric material, wherein the exposed vertical sidewalls form two parallel spacers, wherein each of the two parallel spacers extends the entire length of the cavity, from the bottom surface of the cavity to the open portion of the cavity.
 12. The method of claim 11, wherein the at least one lateral dimension is less than 0.1 mm.
 13. The method of claim 11, wherein the semiconductor substrate comprises silicon. 14.-15. (canceled)
 16. The method of claim 11, wherein the bottom surface comprises the second dielectric material. 17.-18. (canceled)
 19. The method of claim 11, further comprising depositing a layer of a third dielectric material over the back surface of the substrate; and depositing a metal layer on the third dielectric material.
 20. The method of claim 11, wherein a topmost surface of said first dielectric material is planarized such that the topmost surface of the first dielectric material is coplanar with the front surface of the substrate.
 21. The method of claim 11, further comprising forming metal structures within said second dielectric material.
 22. The method of claim 21, wherein said metal structures comprise a strip metallization structure embedded entirely within said second dielectric material.
 23. The method of claim 11, further comprising laminating a transparent layer over the second dielectric material, wherein said laminating comprises forming a binding layer directly on a top surface of said second dielectric material and bonding said transparent layer directly on said binding layer. 